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CY28416
Next Generation FTG for Intel(R) Architecture
Features
* Supports Intel Pentium(R)4-Type CPUs * Selectable CPU Frequencies * Two Differential CPU Clock Pairs * Four 100 MHz Differential SRC Clock Pairs * One CPU/SRC Selectable Differential Clock Pair * One 96 MHz Differential Dot Clock Support * Two 48 MHz Clocks * Four 33 MHz PCI Clocks CPU x2 / x3 SRC x4 / x5 PCI x6 DOT x1 USB x2 REF x2 * Two 33 MHz PCI Free Running Clocks * Low Voltage Frequency Select Input * I2C Support Byte/Word/Block Read/Write Capabilities * Ideal Lexmark Spread Spectrum Profile for Maximum EMI Reduction * 3.3V Power Supply * 48-pin SSOP Package
Block Diagram
XIN XOUT
Pin Configuration
VDD_REF REF
XTAL OSC PLL1
PLL Ref Freq
Divider Network VDD_CPU CPUT[0:1], CPUC[0:1], CPU2/SRC4 VDD_SRC SRCT[0:3], SRCC[0:3]
FS_[C:A] VTT_PWRGD# IREF VDD_PCI PCI[0:3] VDD_PCIF PCIF[0:1] PD
VDD_48MHz
PLL2
DOT96T DOT96C 48MHz0 48MHz1
SDATA SCLK
I2C Logic
SCLK SDATA XOUT XIN VSS_REF REF1/FS_A REF0/FS_C VDD_REF PCI0 PCI1 VDD_PCI VSS_PCI PCI2 PCI3 VSS_PCI VDD_PCI PCIF0/TESTSEL PCIF1/ITPEN VDD_48 48MHz0/FS_B 48MHz1 VSS_48 DOT96T DOT96C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT4 CPUC2_ITP/SRCC4 VDD_SRC VSS_SRC SRCT3 SRCC3 VDD_SRC SRCC2_SATA SRCT2_SATA SRCC1 SRCT1 VSS_SRC SRCC0 SRCT0 VTT_PWRGD#/PD
48-PIN SSOP
CY28416
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
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www.SpectraLinear.com
CY28416
Pin Definition
Pin No. 47,46,44,43 39,38 Name CPUT/C[0:1] CPUT2_ITP/SRCT4 CPUC2_ITP/SRCC4 DOT96T, DOT96C FS_A/REF1 FS_B/48 MHz0 FS_C/REF0 IREF ITP_EN/PCIF1 PCI 48 MHz1 SCLK SDATA SRCT/C[0:3] SRCT2_SATA, SRCC2_SATA TEST_SEL/PCIF0 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSSA VTT_PWRGD#/PD Type O, DIF Differential CPU clock output. O, DIF Selectable Differential CPU or SRC clock output. ITP_EN = 0 @VTT_PWRGD# assertion PIN 39,38 = SRCT4,SRCC4 ITP_EN = 1 @VTT_PWRGD# assertion PIN 39,38 = CPUT2_ITP,CPUC2_ITP O, DIF Differential 96 MHz clock output. I/O, SE 3.3V tolerant input for CPU frequency/REF clock Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O, SE 3.3V tolerant input for CPU frequency/48 MHz clock Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O, SE 3.3V tolerant input for CPU frequency/REF clock Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I A precision resistor is attached to this pin, which is connected to the internal current reference. Description
23,24 6 20 7 42 18 9,10,13,14 21 1 2 26,27,29,30, 34,35 31,32 17 19 45 11, 16 8 33, 37 40 22 48 12, 15 5 28, 36 41 25
I/O, SE Enable SRC4 or CPU2_ITP/PCIF clock. (sampled on the VTT_PWRGD# assertion). 0 = SRC4, 1 = CPU2_ITP O, SE 33 MHz clock output. O, SE 48 MHz clock output. (Uses same control SMBus register as 48 MHz0 to control enable/disable.) I I/O SMBus compatible SCLOCK. SMBus compatible SDATA.
O, DIF Differential Serial reference clock. O, DIF Differential Serial reference clock. Recommended output for SATA I/O, SE, LVTTL input for selecting HI-Z or Normal operation/33 MHz Clock PD 0 = Normal operation, 1 = HI-Z when VTT_PWRGD# is sampled PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND I, PD 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for outputs 3.3V power supply for PLL Ground for outputs Ground for outputs Ground for outputs Ground for outputs Ground for outputs Ground for PLL 3.3V LVTTL Input. This pin is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting power-down (active HIGH) 14.318 MHz Crystal Input 14.318 MHz Crystal Output
4 3
XIN XOUT
I O
Rev 1.0, November 22, 2006
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CY28416
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C input values. For all logic levels of FS_A, FS_B, and FS_C VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, and FS_C transitions will be ignored, except in test mode. initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 1. Frequency Select Table (FS_A FS_B) FS_C 1 0 0 0 0 1 1 1
T
FS_B 0 0 1 1 0 0 1 1
FS_A 1 1 1 0 0 0 0 1
CPU 100 MHz 133 MHz 166 MHz 200 MHz 266 MHz
SRC 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
PCIF/PCI 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
DOT96 96 MHz 96 MHz 96 MHz 96 MHz 96 MHz
USB 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz
RESERVED
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Block Read Protocol Description
Rev 1.0, November 22, 2006
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CY28416
Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 46 .... .... .... .... Description Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N -8 bits Acknowledge from slave Stop Bit 38 46:39 47 55:48 56 .... .... .... ... Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description
Control Registers
Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name CPUT2_ITP/SRCT4 CPUC2_ITP/SRCC4 RESERVED RESERVED SRC[T/C]3 SRC[T/C]2_SATA SRC[T/C]1 SRC[T/C]0 RESERVED Description CPU[T/C]2_ITP/SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable RESERVED, Set = 1 RESERVED, Set = 1 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2_SATA Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable RESERVED, Set = 1
Rev 1.0, November 22, 2006
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CY28416
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Name Spread Selection DOT_96T/C 48 MHz0, 48 MHz1 REF0 REF1 CPU[T/C]1 CPU[T/C]0 CPUT/C SRCT/C PCIF PCI Description 0=Center Spread, 1= Down Spread (Default) DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled 48-MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI3 PCI2 RESERVED RESERVED PCI1 PCI0 PCIF1 PCIF0 PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled RESERVED, Set = 1 RESERVED, Set = 1 PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC[T/C]4 RESERVED RESERVED SRC[T/C]3 SRC2_SATA SRC[T/C]1 SRC[T/C]0 RESERVED Description Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0 RESERVED, Set = 0 Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC2_SATA with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0
Rev 1.0, November 22, 2006
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CY28416
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name RESERVED DOT96[T/C] PCIF1 PCIF0 RESERVED RESERVED RESERVED RESERVED RESERVED, Set = 0 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state Allow control of PCIF2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0 RESERVED, Set = 1 RESERVED, Set = 1 RESERVED, Set = 1 Description
Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C][4:0] Description SRC[T/C] Stop Drive Mode 0 = Driven when SW PCI_STP# asserted,1 = Tri-state when SW PCI_STP# asserted RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]2_ITP PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted
6 5 4 3 2 1 0
0 0 0 0 0 0 0
RESERVED RESERVED RESERVED SRC[T/C][4:0] CPU[T/C]2_ITP CPU[T/C]1 CPU[T/C]0
Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 1 1 1 REF1 REF0 PCIF, SRC, PCI Name RESERVED RESERVED, Set = 0 Test Clock Mode Entry Control 0 = Normal operation, 1 = Hi-Z mode REF1 Output Drive Strength 0 = Low, 1 = High REF0 Output Drive Strength 0 = Low, 1 = High SW PCI_STP# Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF, and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF, and SRC outputs will resume in a synchronous manner with no short pulses. FS_C. Reflects the value of the FS_C pin sampled on power-up 0 = FS_C was low during VTT_PWRGD# assertion FS_B. Reflects the value of the FS_B pin sampled on power-up 0 = FS_B was low during VTT_PWRGD# assertion FS_A. Reflects the value of the FS_A pin sampled on power-up 0 = FS_A was low during VTT_PWRGD# assertion Description
2 1 0
Externally selected Externally selected Externally selected
Rev 1.0, November 22, 2006
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CY28416
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm
Crystal Recommendations
The CY28416 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28416 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
(CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Clock Chip
Ci1
Ci2 Pin 3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal, not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
.
Cs1
X1
X2
Cs2 Trace 2.8pF
XTAL Ce1
Ce2
Trim 33pF
Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
=
1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2
)
Figure 1. Crystal Capacitive Clarification
CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.)
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance Rev 1.0, November 22, 2006
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CY28416
PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs must be held LOW on their next HIGH-to-LOW transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock output must be held with "Diff clock" pin driven high at 2 x Iref, and "Diff clock#" tri-state. If the control register PD drive mode bit corresponding to the
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C
output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are tri-state. Note the example in Figure 3 shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 s after asserting VTT_PWRGD#. PD Deassertion The power-up latency needs to be less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a tri-state condition resulting from power down must be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs are to be enabled within a few clock cycles of each other. Figure 4 is an example showing the relationship of clocks coming up. Unfortunately, we can not show all possible combinations, designers need to insure that from the first active clock output to the last takes no more than two full PCI clock cycles.
PCI, 33 MHz REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0, November 22, 2006
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CY28416
Tstable <1.8 ms
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300 S, >200mV
Figure 4. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
W ait for VTT_PW RGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PW RGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 5. VTT_PWRGD# Timing Diagram
S2 V TT_P W RG D # = Low
S1
D elay >0.25 m s
V DD _A = 2.0V
Sam ple Inputs straps
W ait for <1.8m s S0 S3 V D D_A = off
Power O ff
N orm al O peration
V TT_P W R G D# = toggle
E nable O utputs
Figure 6. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 22, 2006
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CY28416
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 70 150 15 45 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description 3.3 5% Condition Min. 3.135 Max. 3.465 Unit V 3.3V Operating Voltage VDD_A, VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU VILI2C VIHI2C VIL_FS VIH_FS VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPD3.3V Input Low Voltage Input High Voltage FS_[A:C] Input Low Voltage FS_[A:C] Input High Voltage Input Low Voltage Input High Voltage Input Low Leakage Current Input High Leakage Current Output Low Voltage Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max load and freq per Table 6 and Figure 7 PD asserted, Outputs driven PD asserted, Outputs Tri-stated Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA
SDATA, SCLK SDATA, SCLK
- 2.2 0.7 VSS - 0.3 VSS - 0.5 2.0 -5 - - 2.4 -10 2 3 - 0.7VDD 0 - - -
1.0 - VDD + 0.5 0.35 0.8 VDD + 0.5 - 5 0.4 - 10 5 6 7 VDD 0.3VDD 400 70 2
V V V V V V A A V V A pF pF nH V V mA mA mA
Rev 1.0, November 22, 2006
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CY28416
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1- s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Min. 47.5 Max. 52.5 Unit %
TPERIOD T R / TF TCCJ LACC
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy
69.841 - - - 40 9.9970 7.4978 5.9982 4.9985 3.7489 9.9970 7.4978 5.9982 4.9985 3.7489 - - - 175 - - -
71.0 10.0 500 300 60 10.003 7.5023 6.0018 5.0015 3.7511 10.0533 7.5400 6.0320 5.0266 3.7700 160 90 150 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 10.003 10.0533 130 125 300 700 20
ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps mv mv mv V V V % ns ns ps ps ppm ps %
CPU at 0.7V TDC CPUT and CPUC Duty Cycle TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 166-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period 266-MHz CPUT and CPUC Period
TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TPERIODSS 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX TSKEW TCCJ TCCJ T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB SRC TDC TPERIOD TSKEW TCCJ LACC T R / TF TRFM Any CPUT/C to CPUT/C Clock Skew, SSC CPUT/C Cycle to Cycle Jitter CPU2/SRC4 Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period Any SRCT/C to SRCT/C Clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching See Figure 7. Measure SE Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Math averages Figure 7 Math averages Figure 7 Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
660 -150 250 - -0.3 - 45 9.9970 9.9970 - - - 175 -
TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
Rev 1.0, November 22, 2006
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CY28416
AC Electrical Specifications (continued)
Parameter TR TF VHIGH VLOW VOX VOVS VUDS VRB PCI/PCIF TDC TPERIOD TPERIOD THIGH TLOW T R / TF TSKEW TCCJ DOT TDC TPERIOD TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB USB TDC TPERIOD THIGH TLOW T R / TF TCCJ REF TDC TPERIOD Description Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Enabled PCIF/PCI Period PCIF and PCI high time PCIF and PCI low time PCIF and PCI rise and fall times Any PCI clock to Any PCI clock Skew PCIF and PCI Cycle to Cycle Jitter DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy DOT96T and DOT96C Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Duty Cycle Period USB high time USB low time Rise and Fall Times Cycle to Cycle Jitter REF Duty Cycle REF Period See Figure 7. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Math averages Figure 7 Math averages Figure 7 See Figure 7. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Math averages Figure 7 Math averages Figure 7 Condition Min. - - 660 -150 220 - -0.3 - 45 29.9910 29.9910 12.0 12.0 0.3 - - 45 10.4135 - - 175 - - - 660 -150 200 - -0.3 - 45 20.8271 8.090 7.690 0.4 - 45 69.8203 Max. 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 30.0090 30.1598 - - 1.2 500 500 55 10.4198 250 300 780 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 20.8396 10.200 9.950 1.4 400 55 69.8622 Unit ps ps mv mv mV V V V % ns ns ns ns ns ps ps % ns ps ppm ps % ps ps mv mv mV V V V % ns ns ns ns ps % ns
Rev 1.0, November 22, 2006
Page 12 of 14
CY28416
AC Electrical Specifications (continued)
Parameter T R / TF TCCJ Description REF Rise and Fall Times REF Cycle to Cycle Jitter Condition Measured between 0.4V and 2.4V Measurement at 1.5V Min. 0.2 - - 10.0 0 Max. 2.1 1000 1.8 - - Unit ns ps ms ns ns
ENABLE/DISABLE and SETUP TSTABLE Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
Table 6. Maximum Lumped Capacitive Output Loads Clock PCI Clocks 48M Clock REF Clock Max Load 30 20 30 Unit pF pF pF
Test and Measurement Set-up
For Differential CPU and SRC Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CPUT
TPCB
M e a s u re m e n t P o in t
2pF
CPUC IR E F
TPCB
M e a s u re m e n t P o in t
2pF
Figure 7. 0.7V Load Configuration
tDC 3.3V 2.4V 1.5V 0.4V 0V Tr T f Output under Test Probe Load Cap
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Rev 1.0, November 22, 2006
Page 13 of 14
CY28416
Ordering Information
Part Number Lead-free Package Type Product Flow
CY28416OXC CY28416OXCT
48-pin SSOP 48-pin SSOP--Tape and Reel
Commercial, 0 to 70 C Commercial, 0 to 70 C
Package Drawings and Dimensions
48-lead Shrunk Small Outline Package O48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 22, 2006
Page 14 of 14

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